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YDA139
D- 4
STEREO 2.5W DIGITAL AUDIO POWER AMPLIFIER Overview
YDA139 (D-4) is a digital audio power amplifier IC with maximum output of 2.5W (RL=4 )x2ch. YDA139 has a "Pure Pulse Direct Speaker Drive Circuit" which directly drives speakers while reducing distortion of pulse output signal and reducing noise on the signal, and realizes the highest standard low distortion rate characteristics and low noise characteristics as the same class of output digital amplifier IC. In addition, circuit design with fewer external parts can be made depend on the condition of use because corresponds to filter less. YDA139 has the power-down function which can minimize the power consumption in the standby state. In addition, high speed recovery function provided realizes recovery time within 1ms from the power-down state. Moreover, Over-current Protection function for speaker output terminals, IC Thermal Protection function, and POP Noise Reduction function are provided. YDA139 supports both digital signal input and analog signal input.
Features
Maximum output WLCSP25 2.5 Wx2ch (VDDP=VDDA=5.0V, RL=4, THD+N=10%) 1.5 Wx2ch (VDDP=VDDA=5.0V, RL=8, THD+N=10%) SSOP24 2.5 Wx2ch VDDP=VDDA=5.0V, RL=4, THD+N=10% 1.3 Wx2ch VDDP=VDDA=5.0V, RL=8, THD+N=10% Efficiency WLCSP25 91 % (Analog input mode, VDDP=VDDA=5.0V, RL=8, Po=1.5W) SSOP24 88 % (Analog input mode, VDDP=VDDA=5.0V, RL=8, Po=1.5W) Distortion Rate (THD+N) 0.03 % (Analog input mode, VDDP=VDDA=5.0V, RL=8, Po=0.65W) S/N Ratio 99dB (Analog input mode, VDDP=VDDA=5.0V, Gain[1:0]=L,L) Over-current Protection function Thermal Protection function Low voltage Malfunction Prevention function Power-down function by PDN terminal Power-down High speed Recovery function Package Lead-free 25-ball WLCSP (YDA139-WZ) Lead-free 24-pin SSOP (YDA139-EZ)
YDA139 CATALOG CATALOG No.:LSI-4DA139A30 2006.2
YDA139
Terminal configuration
AVDD
AVDD
SDIN
PVDD
OUTPR
5
RIN
PDN
SCLK
OUTPR
OUTMR
4
VREF
MOD1
LRCLK
PVSS
PVSS
3
LIN
MOD0
GAIN1
OUTPL
OUTML
2
AVSS
AVSS
GAIN0
PVDD
OUTPL
1
E
D
C
B
A
<25-ball WLCSP Bottom View>
<24-pin SSOP Top View>
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YDA139
Terminal function
WLCSP25
No. Name A1 OUTPL A2 OUTML A3 PVSS A4 OUTMR A5 OUTPR B1 PVDD B2 OUTPL B3 PVSS B4 OUTPR B5 PVDD C1 GAIN0 C2 GAIN1 C3 LRCLK C4 SCLK C5 SDIN D1 AVSS D2 MOD0 D3 MOD1 D4 PDN D5 AVDD E1 AVSS E2 LIN E3 VREF E4 RIN E5 AVDD (Note) I: Input terminal
SSOP24
I/O Function O Positive differential output terminal Lch 1 O Negative differential output terminal Lch GND GND for output O Negative differential output terminal Rch O Positive differential output terminal Rch 1 Power Power supply for output (non-regulated) O Positive differential output terminal Lch 2 GND GND 2 for output O Positive differential output terminal Rch 2 Power Power supply for output I Gain setting terminal I Gain setting terminal I Word clock input terminal I Bit clock input terminal I Data clock input terminal GND GND for analog circuit I Analog /Digital /Mix mode switching terminal I Analog /Digital /Mix mode switching terminal I Power-down terminal Power Power supply for analog circuit GND GND for analog circuit A Analog input terminal Lch A VREF terminal A Analog input terminal Rch Power Power supply for analog circuit O: Output terminal A: Analog terminal
No. Name 1 AVSS 2 NC 3 LIN 4 MOD0 5 MOD1 6 GAIN0 7 GAIN1 8 NC 9 PVDD 10 OUTPL 11 OUTML 12 PVSS 13 PVSS 14 OUTMR 15 OUTPR 16 PVDD 17 NC 18 SCLK 19 SDIN 20 LRCLK 21 PDN 22 RIN 23 AVDD 24 VREF (Note) I: Input terminal
I/O Function GND GND for analog circuit Non connection. A Analog input terminal Lch I Analog /Digital /Mix mode switching terminal I Analog /Digital /Mix mode switching terminal I Gain setting terminal I Gain setting terminal Non connection. Power Power supply for output O Positive differential output terminal Lch O Negative differential output terminal Lch GND GND for output GND GND for output O Negative differential output terminal Rch O Positive differential output terminal Rch Power Power supply for output Non connection. I Bit clock input terminal I Data clock input terminal I Word clock input terminal I Power-down terminal A Analog input terminal Rch Power Power supply for analog circuit A VREF terminal O: Output terminal A: Analog terminal 3
YDA139
Block diagram
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YDA139
Description of operating functions
Digital Amplifier Function
YDA139 has digital amplifiers with analog and digital input, PWM pulse output, Maximum output of 2.5W(RL=4 )x2ch. Distortion of PWM pulse output signal and noise of the signal is reduced by adopting "Pure Pulse Direct Speaker Drive Circuit" First Stage Amplifier Gain Setting Function YDA139is composed of the first stage amplifier with gain setting control and a 6dB fixed-gain digital amplifier. Gain of the first stage amplifier can be set by GAIN[1:0] terminal. Digital Amplifier Gain Setting (Analog Input -Digital Amplifier Output) GAIN1 GAIN0 Gain Input Sensitivity L L 12dB 800mVrms L H 18dB 400mVrms H L 21.6dB 250mVrms H H 26dB 150mVrms Note H and L indicates logic High and logic Low, respectively. Input Impedance(ZIN) 100k 66.3k 50k 33.3k
Connect a 0.01F or more capacitor to the audio signal input terminals (LIN and RIN) for the rejection of DC signal. The input low region cutoff frequency is calculated by 1/(2xxZINxCIN). When GAIN[0:1]=L,L and CIN=0.01F, the input low region cutoff frequency becomes 159Hz. And, half voltage (VREF) of AVDD terminal voltage is output to the reference voltage terminals (VREF). Connect a 1F or more capacitor to the terminals for voltage stabilization. *When the input low region cutoff frequency is lowered, capacitor that is larger than 0.01F (max. 0.1F) can be connected. However, please note the following points. (1) The pop noise when the power supply is disconnected might become large. Therefore, correspond by following method. After PDN terminal change to "L", disconnect power supply. VREF capacitor is set to CREF=CINx20[F]. (2) The recovery time from the power down becomes long. (Refer to the item "Power Down Function" for relation between the recovery time tPDR and CIN and CREF.)
DAC Function
YDA139 includes a stereo DAC with 44.1kHz, 48kHz/16bit. The output of DAC is amplified by the digital amplifier to output to speakers. The digital signal input supports the following format. Gain from DAC output to the digital amplifier output is fixed to 12dB. The full scale voltage (VFS) of DAC is depending on AVDD terminal voltage (VDDA) and can be found with the following formula: VFS=VDDAx0.56. VFS is amplified 12dB, and it becomes an amplifier output. For example, VFS=1.68V and amplifier output (BTL) =6.72Vpp at VDDA=3V. Do not input the DC signal to YDA139 because built-in DAC doesn't have the DC cutting function. And, do not stop each clock of SCLK, LRCLK and SDIN at the digital input mode and mixing mode.
Digital Signal Input Format (16-bit format with left-justified and a one bit clock delay).
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YDA139
Mode Selection Function
YDA139 has mode selection function for selecting analog input and digital input. In the digital input mode, DAC output signal is output in 12 dB(fixed) of gain. In the analog input mode, analog signal that was input to LIN/RIN is output in a gain in accordance with the setting of GAIN[1:0] terminal. In the mixing mode, the digital input and analog input is mixed and output. MOD[1:0] Setting and Operation Mode
MOD1 L L H H MOD0 L H L H Function Digital Input Mode Analog Input Mode (DAC Power-down) Mixing Mode Reserved
Note) MOD[1:0]=H,H is already reserved by the system.
Power-down Function
When PDN terminal is L, the power-down mode is selected in YDA139. The mode stops all the circuit functions and minimizes power consumption. At this time, the output stage of the digital amplifier is disabled (WL*1). In addition, the High Speed Recovery function allows recovery to the normal operation at 0.8msectPDR when setting PDN to H in the power-down state. Note)*1: "WL" means output disabled (weak pull-down output). The relation between power down recovery time (tPDR) and CIN is as follows.
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YDA139
Protection Function
YDA139 has the following protection functions for the digital amplifier: Over-current Protection function, Thermal Protection function, Low voltage Malfunction Prevention function, and Power supply voltage fluctuation protection function. Over-current Protection function This is a function to make the Over-current Protection Mode by detecting a short-circuiting (Ground short/Power supply short/Short between terminals) in the output stage of digital amplifier and to disable (WL) the output stage of the digital amplifier. When entering the Protection Mode, automatically it returns to the normal operation after a given waiting time(TWT). If short circuiting in the output stage continues, the sequence is repeated: short circuit detection, protection mode (TWT), and automatic recovery. Thermal Protection function This is a function to make the Thermal Protection Mode by detecting extraordinary high temperature of YDA139 and to disable (WL) the output stage of the digital amplifier. This Protection mode is automatically returned to the normal operation state when internal temperature of YDA139 is lowered sufficiently. Low voltage Malfunction Prevention function YDA139 has this Prevention function so as not to cause malfunction in the low power supply voltage. When AVDD voltage becomes lower than VUVLL, the Protection mode is operated to disable (WL) the output stage of the digital amplifier. When AVDD voltage becomes higher than VUVLH, the protection mode is cancelled after a given waiting time and turns into the normal mode. Power supply Voltage Fluctuation Detection function YDA139 has this detecting function so that noise may not be generated from speakers when AVDD voltage was lowered significantly. When AVDD voltage becomes lower than VML, the protection mode is operated to disable (WL) the output stage of the digital amplifier. When AVDD voltage becomes higher than VML, the protection mode is cancelled and turned into the normal operation mode.
Pop noise reduction
When used in Digital Input mode (MOD[1:0]=L,L) and Mixing mode (MOD[1:0]=H,L), cut power off after setting PDN terminal to "L" in order to reduce the pop noise.
Snubber Circuit
When use in power supply voltage 4.5V or more, connect the RC snubber circuit between each output terminal (Lch: between OUTPL and OUTML, Rch: between OUTPR and OUTMR, near IC). The constant and the snubber circuit are as follows. Power supply voltage range 4.5 to 5.25V R 1 C 330pF *1
*1: Use the temperature compensated capacitor.
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YDA139
Application circuit examples
Correspond to Digital input/Analog input/Mixing mode
Snubber circuit is unnecessary. (When use in power supply voltage under 4.5V)
Snubber circuit is necessary. (When use in power supply voltage 4.5V or more.)
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YDA139
Correspond to Digital input mode (Without Snubber circuit
Correspond to Analog input mode (Without Snubber circuit
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YDA139
Electrical Characteristic
Absolute Maximum Ratings*1)
Item Power supply terminal (PVDD) Voltage Range Power supply terminal (AVDD) Voltage Range Input terminal Voltage Range
*2)
Symbol VDDP VDDP VIN
Min. 0.3 0.3 VSS0.3
Max. 6.0 6.0 VDDP0.3
Unit V V V
Allowable dissipation (WLCSP25,Ta=25) PD25 1.26 W Allowable dissipation (WLCSP25,Ta=85) PD85 0.51 W Allowable dissipation (WLCSP25,Ta=25) PD25 1.03 W Allowable dissipation (WLCSP25,Ta=70) PD70 0.41 W Storage Temperature TSTG 50 125 Note) *1:Absolute Maximum Ratings is values which must not be exceeded to guarantee device reliability and life, and when using a device in excess even a moment, it may immediately cause damage to device or may significantly deteriorate its reliability *2: Input terminal means MOD0, MOD1, GAIN0, GAIN1, SCLK, SDIN, LRCLK, and PDN terminal.
Recommended Operating Condition
Item Power Supply Voltage(PVDD) Power Supply Voltage(AVDD) Operating Ambient Temperature Speaker Impedance Symbol VDDP VDDA Ta RL Min. 2.7 2.7 20 4 Typ. 5 5 25 Max. 5.25 5.25 85 Unit V V
DC Characteristics (VSS=0V, VDDP= VDDA =2.7V to 5.25V, Ta=20C to 85C, unless otherwise specified)
Item Symbol Conditions Min. Typ. Output buffer H level output voltage VPOH IOH=100mA VDDP0.1 Output buffer L level output voltage VPOL IOL=100mA AVDD terminal VUVLH 2.2 start-up threshold voltage AVDD terminal VUVLL 2.0 shut-down threshold voltage Power Supply fluctuation VML VREFx1.5*3) shut-down threshold voltage Digital terminal *4) H level input voltage VIH VDDA=5.25V 2.16 Digital terminal *4) H level input voltage VIH VDDA=3.3V 1.32 Digital terminal *4) L level input voltage VIL VDDA=2.7V VREF output voltage VREF VDDA=5V 2.5 Analog mode AVDD terminal IDD VDDA=5V, no load 3.3 consumption current Analog mode PVDD terminal IDD VDDP=5V, no load 2.6 consumption current Digital mode AVDD terminal IDD VDDA=5V, no load 6.1 consumption current Digital mode PVDD terminal IDD VDDP=5V, no load 2.6 consumption current VDDA=VDDP=5V, Consumption current in power-down IPD 0.1 (PDN=L) AVDD terminal + PVDD terminal Ta=25C Note) *3: The value when the AVDD power supply voltage becomes 75% or less is meant. *4: Digital terminal means MOD0, MOD1, GAIN0, GAIN1, SCLK, SDIN, LRCLK, and PDN terminal. Max. 0.05 0.32 Unit V V V V V V V V V mA mA mA mA A
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YDA139
AC characteristics (VSS=0V, VDDP= VDDA =2.7V to 5.25V, Ta=20C to 85C, unless otherwise specified)
Item Symbol SCLK frequency 1/TSCK*5) SCLK Hi time TSCKH SCLK Lo time TSCKL SDIN input set-up time TSDS SDIN input hold time TSDH LRCLK input set-up time TLRS LRCLK input hold time TLRH Note) *51/TSCLK=32Fs64FsFs=44.1kHz, 48kHz Min. 40 40 60 25 60 25 Typ. 3.07 Max. Unit MHz ns ns ns ns ns ns
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YDA139
Analog Characteristics*6) Digital Amplifier Section
Item Maximum output (WLCSP25) Symbol RL=8 PO RL=4 RL=8 PO RL=4 Conditions VDDP=5.0V,VDDA=5.0V,f=1kHz,THD+N=10% VDDP=3.6V,VDDA=3.0V,f=1kHz,THD+N=10% VDDP=5.0V,VDDA=5.0V,f=1kHz,THD+N=10% VDDP=3.6V,VDDA=3.0V,f=1kHz,THD+N=10% VDDP=5.0V,VDDA=5.0V,f=1kHz,THD+N=10% VDDP=3.6V,VDDA=3.0V,f=1kHz,THD+N=10% VDDP=5.0V,VDDA=5.0V,f=1kHz,THD+N=10% VDDP=3.6V,VDDA=3.0V,f=1kHz,THD+N=10% Min. Typ. 1.5 0.8 2.5 1.2 1.3 0.65 2.5 1.0 12 18 21.6 26 0.03 0.03 0.05 0.05 99 98 85 80 90 91 88 CIN =0.01uF , f=200Hz CIN =0.01uF , f=20kHz f=20Hz f=20kHz AVDD=5V 10 20 3/+1 1 1 1 920 300 400 0.8 Max. Unit W W W W W W W W dB dB dB dB % % % % dB dB dB dB dB % % mV mV dB dB dB dB kHz ms ms ms
(VSS=0V, VDDP= VDDA =5.0V, Ta=25C, RL=8, unless otherwise specified)
Maximum output (SSOP24)
GAIN[1:0]=L,L Voltage Gain (Analog input mode) Total Harmonic Distortion Rate (Analog input mode) Total Harmonic Distortion Rate (Digital input mode) Signal /Noise Ratio (Analog input mode) Signal /Noise Ratio (Digital input mode) Channel Separation Ratio Power supply rejection ratio*7) Maximum Efficiency (WLCSP25) Maximum Efficiency (SSOP24) Output offset voltage (Analog input mode) Output offset voltage (Digital input mode) Frequency characteristics (Analog input mode) Frequency characteristics (Digital input mode) AV GAIN[1:0]=L,H GAIN[1:0]=H,L GAIN[1:0]=H,H THD+N THD+N SNR SNR CS PSRR Vo Vo fRES fRES RL=4, PO=1.25W, f=1kHz, GAIN[1:0]=L,L RL=8, PO=0.65W, f=1kHz, GAIN[1:0]=L,L RL=4, PO=1.25W, f=1kHz RL=8, PO=0.65W, f=1kHz RL=8, PO=1.5W, A-Weight, GAIN [1:0]=L,L RL=8, PO=1.5W, A-Weight 1kHz, GAIN[1:0]=L,L VDDP=5.0V, VDDA=5.0V, f=217Hz VDDP=3.6V, VDDA=3.0V, f=217Hz RL=8, PO=1.5W RL=8, PO=1.5W
Carrier clock frequency fSW Over-current protection mode TWT CVREF=1uF, CIN=0.01uF recovery time Start-up time when power supply TPS CVREF=1uF, CIN=0.01uF rise Power-down recovery time TPDR CVREF=1uF, CIN=0.01uF Note) *6:All the values of analog characteristics were obtained by using our evaluation circumstance. Depending upon parts and pattern layout to use, characteristics may be changed. *7:AVDD and PVDD are different power supply. *8:Measurements in VDDP=5V is the value in which snubber circuit (1+330pF) is mounted.
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YDA139
Typical characteristics examples (VDDP= VDDA =5.0V, Ta=25C, RL=8+30H, unless otherwise specified)
THD+N vs Output Power WLCSP25 VDDA=5V VDDP=5V 4+30uH 10
10
THD+N vs Output Power WLCSP25 VDDA=5V VDDP=5V 4+30uH
1 THD+N[%]
THD+N[%]
1
0.1
0.1
0.01 0.0001
0.001
0.01 [W]
0.1
1
10
0.01 0.0001
0.001
0.01 [W]
0.1
1
10
10
THD+N vs Output Power SSOP24 VDDA=5V VDDP=5V 4+30uH
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THD+N vs Output Power SSOP24 VDDA=5V VDDP=5V 4+30uH
1 THD+N [%]
THD+N [%]
1
0.1
0.1
0.01 0.0001
0.001
0.01 [W]
0.1
1
10
0.01 0.0001
0.001
0.01 Power [W]
0.1
1
10
20 15 10 [dBV]
SSOP24 VDDA=5V VDDP=5V
20 15 10 [dBV] 5 0 -5 -10 -15 -20
SSOP24 VDDA=5V VDDP=5V
5 0 -5 -10 -15 -20 100 1000 [Hz] 10000 100000
100
1000 [Hz]
10000
100000
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YDA139
-60 -65 -70 CS [dBV] -75 -80 -85 -90 -95 -100 10 100 1000 [Hz] 10000 100000
CS [dBV]
CS vs SSOP24 VDDA=5V VDDP=5V 1250mW
-60 -65 -70 -75 -80 -85 -90 -95 -100 10
CS vs SSOP24 VDDA=5V VDDP=5V1250mW
100
1000 [Hz]
10000
100000
PSRR SSOP24 VDDA=5V VDDP=5V -40 -50
-20 0
PSRR SSOP24 VDDA=5V VDDP=5V
-60 PSRR [dB]
PSRR [dB]
-70 -80 -90
-40 -60 -80 -100 -120
-100 -110 -120 10 100 1000 PVDD[Hz] 10000 100000
10
100
1000 PVDD[Hz]
10000
100000
Note) The frequency characteristics, channel separation (CS), and power supply rejection ratio (PSRR) are almost equal characteristics regardless of the package.
100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 0
WLCSP25 8+30uH V DDA=5V V DDP=5V
100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 0
WLCSP25 4+30uH V DDA=5V V DDP=5V
[%]
[%]
200
400
600
800 1000 1200 1400 1600 1800 [W]
500
1000
1500 [W]
2000
2500
3000
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YDA139
WLCSP25 8+30uH V DDA=3V V DDP =3.6V
100.0 90.0 80.0 70.0 [%] 60.0 50.0 40.0 30.0 20.0 10.0 0.0 0
100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0
WLCSP25 4+30uH V DDA=3V V DDP=3.6V
[%]
200
400 600 [W]
800
1000
0
200
400
600
800 1000 1200 1400 1600 1800 [W]
100.0 90.0 80.0 70.0 [%] 60.0 50.0 40.0 30.0 20.0 10.0 0.0 0
SSOP24 8+30uH V DDA=5V V DDP =5V
100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 0
SSOP24 4+30uH V DDA=5V V DDP =5V
[%]
200
400
600
800 1000 [W]
1200
1400
1600
500
1000 1500 [W]
2000
2500
100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 0
SSOP24 8+30uH V DDA=3V V DDP =3.6V
100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 0
SSOP24 4+30uH V DDA=3V V DDP =3.6V
[%]
[%]
200
400 600 [W]
800
1000
200
400
600
800 1000 1200 1400 1600 1800 [W]
Note) Measurements in VDDP=5V is the value in which snubber circuit (1+330pF) is mounted.
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YDA139
Package Outline
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YDA139
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YDA139
Notice
The specifications of this product are subject to improvement changes without prior notice.

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